System and method for improving coding gain performance within gigabit phy viterbi decoder
US7139312B2 · kind B2 · utility
8Cited by
6References
25Claims
0Family size
Assignee
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Key dates
| Filing date | May 23, 2002 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Dec 18, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0054
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for improving gain performance of a Viterbi decoder wherein data relating to the best path and a secondary path are stored for the Viterbi decoder. Slicer errors are determined for the best path and the secondary path for current symbols using the stored data and errors for previous symbols are corrected responsive to the determined slicer errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.