Distributed clock network using all-digital master-slave delay lock loops
US7139348B1 · kind B1 · utility
8Cited by
7References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2002 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Sep 4, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A distributed clock circuit for clocking high speed data at various different physical locations on a chip while improving setup and hold times. The clock circuit includes a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked. The clock circuit further includes one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local clock signal with a local data signal, wherein the local clock signal is based on the global clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.