Multiplication logic circuit
US7139788B2 · kind B2 · utility
7Cited by
17References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 2001 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Feb 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5318
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplication logic circuit comprises array generation logic and array reduction logic. The array reduction logic comprises array reduction logic for a first level of array reduction which comprises maximal length parallel counters for reducing maximal length columns. The output of the maximal length parallel counters are then further reduced by a second level of reduction logic comprising logic circuits with asymmetric delays in order to compensate for the differential delays experienced by the outputs of the maximal length parallel counters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.