Pipelining access to serialization tokens on a bus
US7139854B2 · kind B2 · utility
0Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Dec 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/37
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.