Methods and apparatus to support error-checking of variable length data packets using a multi-stage process
US7139963B1 · kind B1 · utility
10Cited by
11References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2003 |
| Grant date | Nov 21, 2006 |
| Priority date | — |
| Expiry date | Jun 30, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0061
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A given data packet is parsed into words and a final partial word that are processed (depending on size) in each of multiple successive stages of logic circuitry. Similarly sized words are processed at one stage of the logic circuit. Smaller and smaller modulo-2 components of the final partial word are processed at successive stages of logic circuitry. Based on this technique of processing modulo-2 components in different stages, the corresponding multi-stage logic circuit can be implemented in a low cost logic circuit such as an FPGA device instead of a custom-masked ASIC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.