Multi-stage EPI process for forming semiconductor devices, and resulting device

US7141478B2 · kind B2 · utility

Assignee

• Legerity, Inc. · US

Inventor

• Chris Speyer · Austin, US

Key dates

• Filing date: Jan 26, 2004
• Grant date: Nov 28, 2006
• Expiry date: Aug 30, 2024

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D10/051

Abstract

The present invention is generally directed to a multi-stage epi process for forming semiconductor devices, and the resulting device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial silicon above a surface of a semiconducting substrate, forming a second layer of epitaxial silicon above the first layer of epitaxial silicon, forming a third layer of epitaxial silicon above the second layer of epitaxial silicon, forming a trench isolation region that extends through at least the third layer of epitaxial silicon and forming a portion of a semiconductor device above the third layer of epitaxial silicon within an area defined by the isolation region. In one illustrative embodiment, the device comprises a substrate, a first layer of epitaxial silicon formed above the substrate, a second layer of epitaxial silicon formed above the first layer of epitaxial silicon, a third layer of epitaxial silicon formed above the second layer of epitaxial silicon, a trench isolation region that extends through at least the third layer of epitaxial silicon, the trench isolation region defining an active area, and at least one component of a semiconductor device form…