Methods for manufacturing a soft error and defect resistant pre-metal dielectric layer
US7141503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jan 21, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a pre-metallization layer on an underlying micro-structure, and a corresponding micro-structure formed by the method. The micro-structure may be a semiconductor circuit and/or a Micro-Electro-Mechanical Systems (MEMS) device. A first layer of undoped silicate glass is deposited on a micro-structure. Then, a layer of phospho silicate glass is deposited on the first layer of undoped silicate glass. This combination is then densified by applying a temperature to the combination that is sufficient to densify the layer of phospho-silicate glass, while being below the glass flow temperature. After densification, a second layer of undoped silicate glass is deposited on the densified layer of phospho silicate glass. Finally, the upper surface of the second layer of undoped silicate glass is polished using a chemical mechanical polishing process. The result is a dielectric layer of high density and low stress, and that reduces soft errors and defects.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.