Integrated circuit package configuration incorporating shielded circuit element structure

US7141883B2 · kind B2 · utility

Assignee

• Silicon Laboratories Inc. · US

Inventors

• Derrick Wei · Hengshan, TW
• Ying Shi · Saratoga, US
• Kevin Smith · Grove City, US
• Steven P. Proffitt · Austin, US
• Axel Thomsen · Austin, US
• David Pietruszynski · Austin, US
• Ligang Zhang · Huangyang, CN

Key dates

• Filing date: Jun 18, 2003
• Grant date: Nov 28, 2006
• Expiry date: Jun 18, 2023

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3025
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formed around the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.