Integrated circuit implementation for power and area efficient adaptive equalization
US7142596B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jun 17, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jan 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45731
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-s interference (ISI), providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.