Analog unidirectional serial link architecture
US7142624B2 · kind B2 · utility
4Cited by
27References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2005 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Sep 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present analog invention is related to a unified digital architecture comprising logic transmitter portions and logic receiver portions. A unified serial link system and method for transmitting digital data across wired media including a transmitter and a receiver portion is provided, one of the transmitter portion and receiver portion comprising a phase locked loop (PLL) circuit. The PLL circuit comprises a voltage control oscillator, a frequency divider, a phase-frequency detector, a charge pump and a multi-pole loop filter. One embodiment comprises a dual loop PLL having a digital coarse loop and an analog fine loop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.