Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure
US7143021B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Mar 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits). If the handles (SH's) of two or more subcircuit parts point to a same, state-describing S-part, where the latter points to a merged I-circuit, and where the latter points to a merged T-circuit, then it can be determined by this that the respective subcircuit parts are both isomorphic and substantially iso-static and can…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.