Method for supporting improved burst transfers on a coherent bus
US7143246B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 16, 2004 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Dec 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a multiprocessor system, comprising master and slave processors, a cache coherency controller, and address concentration devices; a method for improving coherent data transfers is described. A command transaction is generated, and a subsequent command from an initiator. Tags added to the responses or further request responses, stream on high-speed busses. Snoops and accumulated snoops expand on cacheline requests as each processor separates burst commands into multiple cacheline requests. Address concentrators containing a cacheline queue function, funnel transaction requests to a global serialization device, where a queuing process prioritizes indicia and coordinates the results among the processors. The cache issues a single burst command for each affected line. System coherency, performance, and latency improvements occur. Additional support for burst transfers between coherent processors is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.