Data storage system
US7143306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Jul 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system interface having a cache memory and a plurality of directors. Each one of the plurality of directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.