Alignment of recovered clock with data signal
US7143312B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2003 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Apr 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/043
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A recovered clock signal is aligned (“eye centered”) with a data signal from which it is recovered by intentionally varying one of the factors or parameters that causes misalignment. For example, if a loop circuit (i.e., a phase-locked loop or a delay-locked loop) is used to recover the clock signal, charge pump current mismatch in the charge pump of the loop circuit is normally one factor in clock-data misalignment, and is also a parameter that can be manipulated. During a test mode, the current mismatch can be varied to obtain the best error rate, which signifies the best clock-data alignment. The test mode can be implemented using built-in self-test circuitry already on the device to transmit test data and then to receive it and analyze it for errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.