System and method for multi processor memory testing
US7143321B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2000 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | Apr 29, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing the memory in a system with two or more processing units is provided that generally involves the following acts. The memory is divided into two or more sections—one for each of the two or more processing units. Thus, each processing unit has an associated memory section. The memory is then checked with each memory section being checked with its associated processing unit. The act of checking the memory includes causing the address of a first encountered faulty location to be stored and causing a flag to be set in response to encountering a second faulty location. Finally, it is determined whether the flag has been set after the memory is checked. If so, a walk-through routine is then performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.