Capping processor utilization
US7143411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Nov 28, 2006 |
| Priority date | — |
| Expiry date | May 22, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus, system, and method allow for capping processor utilization in a computer system. The processors are typically central processing units (CPUs) under control of a system scheduler. The system scheduler controls which of the CPUs will run specific processes. The processes may run according to a predefined priority assigned to each of the processors. A processor bandwidth waster includes a software routine that operates as an infinite loop in one or more of the CPUs. The bandwidth waster may have the highest priority of any process in the computer system such that the bandwidth waster always runs on the CPUs unless a specific action is taken to turn off, or stop, the bandwidth waster. Data are gathered from the CPUs, including time of operation of any bandwidth waster, and the gathered data are used to compute a bill for operation of the computer system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.