Self-bypassing voltage level translator circuit
US7145364B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Jul 31, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/102
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.