Frequency-controlled DLL bias
US7145373B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Nov 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for controlling bias of a delay-locked loop includes a peak detector and a comparator in the form of a differential amplifier. The peak detector detects the amplitude of a signal output from the DLL, and the comparator compares the DLL output signal amplitude to a reference signal. The comparator then generates a tail current control signal for the DLL based on a result of the comparison. In one embodiment, the reference signal is indicative of a predetermined tail current value for the DLL, and the tail current control signal adjusts delay of the DLL to equal the predetermined tail current value. Preferably, the tail current control signal maintains the DLL signal output at a substantially constant amplitude in spite of frequency variations and may also be used to set the voltage swing for the DLL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.