Resonant clock distribution for very large scale integrated circuits
US7145408B2 · kind B2 · utility
35Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2003 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Mar 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit. At least one additional inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, which may distributed throughout the integrated circuit, has an inductance value selected to resonate with impedance of the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.