Method and apparatus for optimal write restore for memory
US7145822B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 3, 2005 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment of the present invention a memory subsystem comprises a column and a column select signal line. The column comprises at least one bit line and a write precharge circuit. The write precharge circuit is operable to provide at least a portion of a charge on the at least one bit line. The column select signal line is operable to provide a column select signal selecting the column for a write operation. The write precharge circuit is gated with the column select signal line such that the column select signal is communicated to the write precharge circuit upon selection of the column for the write operation. The write precharge circuit is operable to at least partially restore the charge on the at least one bit line upon receipt of the column select signal after the write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.