Method and system for parallel hash transformation for an address input
US7145911B2 · kind B2 · utility
6Cited by
6References
24Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 5, 2002 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Oct 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method for performing a parallel hash transformation in a network device to generate a hash pointer for an address input. The method includes the step of receiving an address input. The address input is apportioned among a plurality of hashing units. The hashing units are configured to operate in parallel. A hash transformation is executed on the apportioned address inputs in parallel, resulting in a corresponding plurality of hashing unit outputs. The hashing unit outputs are combined to generate a hash result corresponding to the address input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.