SIMD processor with scalar arithmetic logic units
US7146486B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2003 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Jul 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3893
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality of successive, adjacent time intervals. Each unit provides an output data item in the time interval in which the unit performs the operation and provides a processed data item in the last of the successive, adjacent time intervals. The special function unit provides a special function computation for the output data item of a selected one of the scalar units, in the time interval in which the selected scalar unit performs the operation, so as to avoid a conflict in use among the scalar units. A vector processing unit includes an input data buffer, the scalar processor, and an output orthogonal converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.