Logic circuit optimizing method, logic circuit optimizing device and logic circuit composing device
US7146582B2 · kind B2 · utility
2Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2004 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Mar 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dividing flip-flop FF2 is inserted in a cluster C of which the cluster length exceeds a predetermined cluster length. The flip-flop inserted cluster C is re-clustered, generating subdivided clusters C1 and C2. Therefore, the degree of freedom is increased in allocating clusters to a variable logic element such as an FPGA in a logical emulation device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.