Method and apparatus for configuring a programmable logic device
US7146598B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 19, 2002 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for configuring multiple first programmable logic devices from a single memory includes a microprocessor, and a second programmable logic device containing the interface logic for the first programmable device and the microprocessor. The present invention allows multiple FPGAs to be programmed from a single memory structure under the control of the microprocessor thereby using fewer components than systems dedicating a separate memory to each FPGA. A communications port allows new configurations to be downloaded to the microprocessor memory. In addition, the present invention can be used in combination with standard systems with each FPGA having its own memory, with the microprocessor being able to select between the central microprocessor memory and the local memory for programming each FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.