Intrusion detection accelerator
US7146643B2 · kind B2 · utility
100Cited by
73References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2002 |
| Grant date | Dec 5, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/554
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Signatures of character strings in a document which may indicate a possible intrusion into or attack on a networked computer system or node thereof or other security breach are detected at high speed using a hardware accelerator within the environment of a hardware parser accelerator. An interrupt or exception can thus be issued to a host CPU before a command which may constitute such a security breach, intrusion or attack can be made executable by parsing of a document. The CPU can initiate network control measures to prevent or limit the intrusion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.