Method and apparatus for using a capacitor array to measure alignment between system components
US7148074B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Nov 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.