Controller arrangement with automatic power down
US7148642B2 · kind B2 · utility
15Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2006 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Apr 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02P23/0004
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A control circuit is described in which a single input terminal receives digital control signals and analog control signals. In accordance with the principles of the invention, the control circuit includes an automatic power down circuit to place the control circuit into a low power draw or “sleep” mode whenever predetermined conditions are present. The automatic power down circuit monitors the single input terminal and when no demand for motor operation occurs for a predetermined period of time, the automatic power down circuit operates to place the control circuit into the low power draw mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.