Impedance matching circuit and method
US7148720B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Dec 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An impedance matching circuit has comparator, counter, two current sources, semiconductor resistance device, and variable MOS impedance device. The current sources are respectively coupled to an internal impedance device and an external impedance device. The comparator has two input terminals and an output terminal. The input terminals of the comparator are coupled to the internal and external impedance devices. The output terminal of the comparator is coupled to the counter. The variable MOS impedance device is coupled between the counter and the semiconductor impedance, and is controlled by the counter. When the voltages of the internal impedance and the external impedance are not matched, the variable MOS impedance device can provide the compensating impedance by adjusting the counting value of the counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.