Apparatus, method and limited set of messages to transmit data between scheduler and a network processor
US7149212B2 · kind B2 · utility
22Cited by
14References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2002 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Dec 28, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/22
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An interface to interconnect Network Processor and Scheduler chips in a multi-chip system includes a limited set of messages and circuit arrangements to generate the limited set of messages. The messages include FlowEnqueue.request, FlowEnqueue.response, PortEnqueue.request and PortStatus.request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.