Method and apparatus for reducing oscillator pull in a CMOS wireless transceiver integrated circuit
US7149246B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2003 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Mar 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A monolithic transceiver integrated circuit that includes a substrate, a transmitter subsystem of one or more subcircuits on the substrate, and a receiver subsystem of one or more subcircuits on the substrate. Also included is a bias current supply coupled to the receiver and transmitter subsystems to provide bias current. The bias current supply includes a first bias circuit on the substrate coupled to, and to supply bias current to, a first subcircuit of the transmitter subsystem. The first bias circuit includes a first current modulator having a first switch input to indicate that the bias current is to start or stop being supplied to the first subcircuit. The first current modulator is to control the rate of change of supplied bias current in response to the first switch input. The first subcircuit may be a power amplifier. The control of the rate of change reduces oscillator pull in at least one oscillator included in the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.