2D FIFO device and method for use in block based coding applications
US7149362B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2002 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Aug 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/42
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Coding, transcoding and iterative filtering methods and apparatus are described wherein a 2D FIFO is used to implement CACLA processing, and wherein the processing methods are block-oriented. A block-by-block processed input image or input coded image, which is delayed in an arbitrary number of lines and columns, is provided such that the output image is produced in a block-by-block schedule at a reduced or minimal memory access and memory size cost. A 2D FIFO which is memory-efficient in image block coding and decoding applications is described. The 2D FIFO has an associated scheduling mechanism for enabling delay of a block-by-block coded input signal, such as an image, in an arbitrary number of lines and columns, such that the output image is produced in a block-by-block schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.