Method for time-domain synchronization across a bit-sliced data path design
US7149916B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 22, 2004 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | May 10, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A bit slice data path design is provided. Multiple chips are coupled to a data bus and configured to process a slice of data for the data bus. One chip in the design is designated as a master chip and the other chips are designated as slaves. A master chip sends a signal from a first time domain to a second time domain through a synchronization circuit. When the signal has been synchronized to the frequency of the second time domain, the signal is sent to the slave chips through a connection. The signal is also looped back to the second time domain in the master chip so that the signal reaches the second time domain in the master and slave chips in the same clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.