Deterministic error recovery protocol
US7149920B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2003 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Jun 22, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2001/0092
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Disclosed are an error recovery method and system for use with a communication system having first and second nodes, each of said nodes having a receiver and a sender, the sender of the first node being connected to the receiver of the second node by a first cable, and the sender of the second node being connected to the receiver of the first node by a second cable. The method comprising the step of after one of the nodes detects an error, both of the nodes entering the same defined state. In particular, the receiver of the first node enters an error state, stays in the error state for a defined period of time T, and, after said defined period of time T, enters a wait state. Also, the sender of the first node sends to the receiver of the second node an error message for a defined period of time Te, and after the defined period of time Te, the sender of the first node enters an idle state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.