Assisted memory device for reading and writing single and multiple units of data
US7149950B2 · kind B2 · utility
116Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 12, 2003 |
| Grant date | Dec 12, 2006 |
| Priority date | — |
| Expiry date | Mar 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device comprises a memory array in which a plurality of codewords is stored. Each codeword comprises an error correction code and a data block that comprises a plurality of units of data. The device further comprises an error code correction module coupled to the memory array. When multiple units of data are to be read from the device for an address, a codeword stored in a location associated with the address is fetched from the memory array, the error code correction module decodes the codeword and corrects any errors in the data block for that codeword, and the multiple units of data are read from the corrected data block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.