Semiconductor device and manufacturing method thereof
US7151015B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 11, 2001 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jul 3, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6721
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There has been a problem that the manufacturing process is complicated and the number of processes is increased when a TFT with an LDD structure or a TFT with a GOLD structure is formed. In a method of manufacturing a semiconductor device, after low concentration impurity regions (24, 25) are formed in a second doping process, a width of the low concentration impurity region which is overlapped with the third electrode (18c) and a width of the low concentration impurity region which is not overlapped with the third electrode can be freely controlled by a fourth etching process. Thus, in a region overlapped with the third electrode, a relaxation of electric field concentration is achieved and then a hot carrier injection can be prevented. And, in the region which is not overlapped with the third electrode, the off-current value can be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.