Low noise charge pump for PLL-based frequence synthesis
US7151413B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 2004 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Feb 22, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low noise charge pump for use in a PLL-based frequency synthesizer. The charge pump includes a timing controller and a plurality of charge-pump circuits. The timing controller receives a reference signal to generate a plurality of enable signals having non-overlapping phases, where the frequency of each enable signal is equal to that of the reference signal divided by the number of the enable signals. The charge-pump circuits are coupled in parallel and operate in a time-interleaved manner according to the enable signals. In response to a first and second control signal, the charge-pump circuits are able to generate respective output currents which are multiplexed together to form a charge-pump current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.