Sample clock extracting circuit and baseband signal receiving circuit
US7151812B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2002 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Sep 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/042
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A sample clock extracting circuit comprises including a number-of-change point memory, a number-of-change point updating circuit and an output clock phase determining circuit. The number-of-change point memory stores a number-of-change-point information set every N types of clock phases each having a frequency equivalent to N times a symbol transmission rate of an input baseband signal. The number-of-change point updating circuit updates the number-of-change point information stored in the number-of-change point memory about a clock phase related to timing thereof when a rising change point or a falling change point occurs in the baseband signal. The output clock phase determining circuit determines a clock phase directly or indirectly indicative of a sample clock phase for the baseband signal based on the number-of-change-point information stored in the number-of-change point memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.