Method for providing power management on multi-threaded processor by using SMM mode to place a physical processor into lower power state
US7152169B2 · kind B2 · utility
25Cited by
37References
39Claims
0Family size
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Key dates
| Filing date | Nov 29, 2002 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jan 11, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3228
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the physical processor is placed in a low power state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.