Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating
US7152170B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 2003 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing circuits that are associated with the operation of threads in an SMT processor can be configured to operate at different performance levels based on a number of threads currently operated by the SMT processor. For example, in some embodiments according to the invention, processing circuits, such as a floating point unit or a data cache, that are associated with the operation of a thread in the SMT processor can operate in one of a high power mode or a low power mode based on the number of threads currently operated by the SMT processor. Furthermore, as the number of threads operated by the SMT operator increases, the performance levels of the processing circuits can be decreased, thereby providing the architectural benefits of the SMT processor while allowing a reduction in the amount of power consumed by the processing circuits associated with the threads. Related computer program products and methods are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.