Embedded sequence checking
US7152193B2 · kind B2 · utility
9Cited by
1References
34Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2002 |
| Grant date | Dec 19, 2006 |
| Priority date | — |
| Expiry date | Jan 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F21/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit generally including a control function and a checksum function is disclosed. The control function may be configured to assert (i) a start signal in response to a signal having a predetermined sequence of values matching an entry value and (ii) a stop signal in response to the signal matching an exit value. The checksum function may be configured to (i) generate a checksum value for the signal between assertions of the start signal and the stop signal and (ii) generate a result signal in response to comparing the checksum value with an expected value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.