Double-gated transistor circuit
US7154135B2 · kind B2 · utility
4Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Nov 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.