Comparators capable of output offset calibration
US7154294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jul 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled to the differential logic signals at the output terminals of the MCML circuit to amplify the differential logic signal and generating a comparison resulting signal. By adjusting the digital calibration codes applied to the calibration unit, current on the output terminals can be adjusted, such that output offsets at the output terminals of the MCML circuit 10 can be eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.