Latch circuit including a data retention latch
US7154317B2 · kind B2 · utility
12Cited by
4References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2005 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jan 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A latch circuit 2 is described including a function path latch 4, 6, which may be in the form of a standard flip-flop, together with a data retention latch 12, 14. The reset signal nreset and the scan enable signal SE are used to control these latches to perform reset, scan, save and restore functions. The save and restore functions serve to save a data value dv from the functional path latch 4, 6 into the data retention latch 12, 14 and restore this value such that the functional path latch can be powered down without a loss of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.