Integrated circuit delay chains
US7154324B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2004 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Dec 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00143
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Delay chain circuitry is provided. The delay chain circuitry has a number of delay chain inverters. Each delay chain inverter is connected in series with a load resistor and has an associated capacitor between its input and ground. The electrodes of each capacitor may be formed from metal separated by non-gate-oxide dielectric to maintain accurate capacitor tolerances. A stable current source such as a bandgap reference current source may apply a current to a sensing resistor. The resulting bias voltage is indicative of changes in resistance due to changes in operating temperature. A temperature compensation circuit may use the bias voltage to produce temperature-compensation control signals. The temperature-compensation control signals are applied to the delay chain inverters to adjust their resistances and compensate for temperature-induced changes in the resistances of the load resistors. This ensures that the delay of the delay chain is independent of operating temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.