Clock generator and related biasing circuit
US7154352B2 · kind B2 · utility
6Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2004 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Dec 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock generator capable of providing reduced low-frequency jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.