DNL/INL trim techniques for comparator based analog to digital converters
US7154421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2004 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Aug 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/363
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A trimmable comparator. The novel comparator includes a first circuit for comparing first and second input signals and in accordance therewith generating first and second output signals, and a second circuit for adding an adjustable current to the first output signal such that the comparator is in a transition state when the first and/or second input signals are at desired levels. The comparator may also include a third circuit for adding an adjustable current to the second output signal. In the illustrative embodiments, the second and third circuits are implemented using adjustable current sources with trimmable resistors, or using digital to analog converters. The novel comparators may be used in an analog to digital converter to allow the converter thresholds to be adjusted to desired levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.