Video apparatus, notably video decoder, and process for memory control in such an apparatus
US7154559B2 · kind B2 · utility
0Cited by
8References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2002 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Aug 7, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/426
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A video apparatus has a digital decoder having a first memory on an internal bus and linked to an OSD circuit and to a second memory via a main bus.The video apparatus comprises means for realizing a DMA transfer between the first memory and the second memory.A process for controlling such a video apparatus is also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.