Packet transfer device, semiconductor device, and packet transfer system
US7154890B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Dec 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/602
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet transfer device has a layer 2 switch and performs switching by referring to header information of a 3rd layer and higher layers. Input/output ports receives packets from and transmits packets to other devices connected to the packet transfer device. A header information extracting circuit extracts header information belonging to a 3rd layer (network layer) and higher layers of a network protocol from packets inputted from the respective input/output ports. A table stores header information and control information corresponding to the header information in association with each other. A control information acquiring circuit acquires control information corresponding to the header information extracted by the header information extracting circuit from the table. A processing circuit processes packets based on the control information acquired by the control information acquiring circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.