Cascaded delay locked loop circuit
US7154978B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2001 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | May 31, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop frequency synthesizer in several embodiments uses a primary delay line element (24) and one or more secondary delay elements (162 . . . 164, 270, 310). In one embodiment, a main delay line (24) is used to coarsely select a frequency output while a secondary delay element (162 . . . 164, 270, 310), either passive or active, is used to increase the resolution of the primary delay line (24). In the passive embodiment, a coarse and fine frequency selection is possible by selecting components from the output taps of the main delay line (24) as a driving signal for the passive secondary delay element (310) to provide the coarse adjustment and selecting an output from the secondary delay element (310) to provide the fine selection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.