Method and apparatus for computer memory protection and verification
US7155590B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Apr 5, 2001 |
| Grant date | Dec 26, 2006 |
| Priority date | — |
| Expiry date | Jan 17, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for computer memory protection and verification. In one example, the apparatus is a secure memory device (SMD) including means to independently read the program memory device and compute and store a signature or other means of verification of binary content of the program memory device, means to compare binary program memory content to binary program memory content stored in the program memory device, and means to disable reading and writing of the program memory device if predetermined conditions do not occur. A previously stored signature of program memory content may be used as means of verification of previous program memory content. A secure memory device may be constructed as a single securely enclosed unit that is tamperproof and that has electrical connections available only for purpose of connection with an apparatus that accepts a program memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.